Four Masks: Why China's DUV Chip Push Costs More Than EUV

Chinese semiconductor manufacturers are producing advanced chips at a higher cost per unit to work around export restrictions on extreme ultraviolet lithography equipment. The country’s foundries rely on older deep ultraviolet tools that require multiple exposure steps to print complex designs. This method increases the time required for production and raises the likelihood of defects, resulting in higher bills for finished silicon.

Export controls have prevented ASML, the sole maker of EUV machines, from selling its most advanced equipment to China. These tools use 13.5 nanometer wavelength light to print the finest features on modern processors. Analysts estimate the technological gap between China and Western competitors in this area stands at five years or more. The lack of access to these specific machines has become the primary bottleneck for the country’s chip industry.

Despite these limits, Chinese firms have achieved measurable progress. A 2023 teardown of the Huawei Mate 60 Pro revealed that its Kirin 9000S processor was manufactured by SMIC using a second-generation 7 nanometer process without EUV. Subsequent analysis of the Kirin 9030 processor indicates that SMIC has moved its DUV-based process closer to the density levels associated with 5 nanometer manufacturing. However, the process still lags behind the leading nodes from TSMC and Samsung.

The technique enabling this progress is known as multiple patterning. Instead of printing an intricate layer in a single pass, manufacturers split the design into several simpler patterns and build the layer step by step. Chris Mack, co-founder and CTO of Fractilia, noted that industry standards previously held that three exposures on a 193 immersion tool cost roughly the same as one EUV exposure. Mack stated that at four masks, EUV becomes the cheaper option.

Quality issues arise with each additional exposure step. Every new pattern must align precisely with previous etchings, leading to accumulated overlay errors and process variation. Designers often add space around features to compensate for these errors, which enlarges the chip and reduces the number of dies per wafer. Since wafers cost tens of thousands of dollars, this reduction in die count is a costly outcome. Mack emphasized that manufacturers sell die, not wafers.

Memory production data illustrates the efficiency gap. A June report from Morgan Stanley estimated that Chinese DRAM maker CXMT produces only about one-third as many bits per wafer as Western rivals. The bank described lithography access as a hard ceiling for Chinese memory development. Mack also cautioned that node labels such as 5 nanometer or 3 nanometer have limited meaning on their own. He noted that SMIC’s N+3 process, while a step forward, remains less scaled than established 5 nanometer processes from Samsung and TSMC.

DUV technology still has room for expansion. Micron developed its 1-alpha DRAM without EUV by using multiple patterning and tight process control. Mack said Micron pushed 193 nanometer tools farther than any other memory maker. Morgan Stanley considers CXMT’s planned move to 1-alpha DRAM, intended for HBM3e, achievable without EUV. Douglas Fuller, a researcher at Copenhagen Business School, expects advanced packaging to allow firms to use DUV for the latest DRAM generations by the end of the decade.

Mack added that China could make substantial progress if it had the full 193 immersion ecosystem and designed products around it. He stressed that memory production is much easier than logic chip fabrication. Micron eventually turned to EUV for its 1-gamma DRAM, which delivers more than 30% greater bit density per wafer than the previous 1-beta generation. Mack said he would be hard pressed to believe a 3 nanometer or 2 nanometer node could be economically viable without EUV.

Chinese chipmakers will continue to push DUV while accepting larger dies, poorer yields, or longer manufacturing times. They can also add production capacity. Morgan Stanley assumes CXMT will stay on 1-alpha without EUV and will lift its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 through new greenfield capacity. The bank expects China’s AI chip self-sufficiency to rise from 42% in 2025 to 70% by 2030, while gaps in EUV, HBM, and advanced software remain.