Micron plans wafer bonding for 2027 G11 NAND
The technology aims to double storage density to 42 Gb/mm2 and boost I/O speeds to 5,400 MT/s.
By Giovanni Serrano ·

Micron intends to ramp production of its G11 3D NAND flash in the second half of 2027, marking a shift toward wafer-on-wafer bonding to increase storage density. The company stated at an event this week that the new generation will deliver approximately twice the storage density of its current technology.
Specific figures indicate the shift will move capacity from 21 Gb/mm2 to 42 Gb/mm2 in triple-level-cell form. Input/output speeds are projected to rise from 3,600 MT/s to 5,400 MT/s, a 50 percent increase. Micron also expects energy consumption per bit to drop by more than 25 percent.
Scott DeBoer, Micron president and chief technology and products officer, confirmed the design relies on bonding two separate wafers together. One wafer will house the NAND array, while the other contains the peripheral circuitry and I/O. This method allows the company to optimize each component with a process tailored to its specific function, rather than using a single design for the entire chip.
DeBoer described G11 as the world's most advanced NAND. He noted that Micron had previously promised to adopt the technology once it became cost-effective and relevant to product specifications. He characterized the current timing as appropriate for that transition.
The new chips will feature more than 400 layers, although Micron has not disclosed the exact count of active wordline layers or memory decks. The company stated the design will have an industry-leading memory cell pitch. This suggests the density improvement results from both additional layers and smaller cell dimensions.
Micron stated it will share further technical details in 2027, closer to the start of high-volume production. The company plans to continue scaling in all three dimensions beyond G11. It is developing high-mobility materials, ultra-dense cell architectures, and more energy-efficient data paths to improve transistor characteristics and reduce energy needs.
DeBoer said the company has a strong roadmap for future generations but did not provide specific architectural details or production schedules for those models. He noted that the industry continues to scale by adding layers and shrinking cell dimensions, a trend expected to persist as demand for NAND-based storage remains strong.
Source: Tom's Hardware





